Staff STA Engineer

Position Overview

We are seeking a highly skilled Staff STA Engineer to drive full‑chip timing closure across complex SoC and analog/mixed‑signal (AMS) integration projects. The ideal candidate will have deep expertise in static timing methodology, asynchronous clock domain interactions, analog–digital interface timing, and signoff flows. This role collaborates closely with SoC digital design, physical design, analog IP designers, EDA vendors, and cross‑functional engineering teams to ensure robust timing closure, silicon predictability, and first‑silicon success.

Key Responsibilities

Static Timing Analysis & Signoff

• Own full‑chip STA signoff, including constraints development, timing setup, analysis, debugging, and closure at multiple PVT corners.
• Develop, validate, and maintain SDC constraints, including false paths, multi‑cycle paths, generated clocks, and mode/corner definitions.
• Perform timing correlation and optimization across synthesis, APR (P&R), and signoff tools.
• Analyze and resolve complex timing issues such as cross‑clock domain timing, hold/setup violations, and on‑chip variation.

Collaboration with SoC & Analog Teams

• Work closely with SoC designers to interpret timing architecture, pipeline strategies, clocking schemes, and interface timing budgets.
• Partner with analog/mixed‑signal design teams to model analog–digital boundaries, including:
  • IO pad timing
  • PLL, DLL, ADC/DAC timing behavior
  • Level shifters, isolation cells
  • Custom timing arcs and Liberty model generation
• Validate timing assumptions between analog and digital components and ensure signoff alignment.

EDA Tools, Flow, and Methodology

• Drive timing methodology improvements, including:
  • STA automation
  • Multi-mode multi-corner (MMMC) flows
  • IR drop & EM‑aware timing
  • Liberty modeling and constraint quality checks
• Work with EDA vendors to evaluate and enhance signoff timing tools and flows.

Silicon Validation & Debug

• Support post‑silicon timing analysis, correlation, and root-cause debug of timing‑related issues.
• Provide guidance to PD and design teams based on silicon learnings.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of hands-on experience with STA in large SoC or mixed‑signal products.
• Expert-level knowledge of:
  • PrimeTime, Tempus, or equivalent STA tools
  • SDC constraint writing and timing signoff methodology
  • Clocking architecture, CDC concepts, and asynchronous boundaries
  • OCV/AOCV/POCV and statistical timing
• Strong experience collaborating with analog IP teams and handling AMS/digital interface timing.
• Solid understanding of SoC physical design flows, including placement, routing, CTS, ECO closure.
• Familiarity with scripting languages (Tcl, Python, Perl) for automation.
• Excellent communication skills to work across digital, analog, physical design, and architecture groups.

Preferred Qualifications

• Experience with high-speed IO, SerDes, memory interfaces, or custom analog IPs.
• Knowledge of Liberty modeling (CCS/ECSM) and timing characterization.
• Exposure to power-aware timing, UPF/CPF, and multi-voltage domain design.
• Strong problem-solving skills and ability to drive cross-team decision-making.